1. Field of the Invention
The present invention relates to a field effect transistor and a method for manufacturing the field effect transistor.
2. Related Art
Conventionally, the driving current per unit gate length is increased by reducing the gate length of each transistor and thinning each gate insulating film, so as to form more sophisticated CMOS circuit devices with higher performance. In this trend, the transistor size that can obtain the necessary driving current has become smaller, and high integration can be achieved. At the same time, the driving voltage has become lower, and the power consumption per unit device can be reduced.
However, as the gate lengths have become smaller, the technical hurdle that needs to be crossed to achieve higher performances is rapidly becoming higher. To counter this difficult situation, a structure including two or more gate electrodes is effective. For example, a double-gate structure having gate electrodes above and below the channel, and a gate-all-around structure that has gate electrodes surrounding the channel are effective. Among gate-all-around structures, those with channels having diameters of 10 nm or less are also known as nanowire transistors. Structures each having a gate formed at either side of the channel (fin) of a mesa structure that is perpendicular to the substrate and has a plate-like shape are called Fin FETs, and structures each having a gate formed on each of the three faces (the two sidewalls and the upper face) are called tri-gate FETs. Those structures are collectively called multi-gate structures. By virtue of the gates, each of those structures has greater electro-static controllability of the channel carriers than that of a regular planar-type single-gate structure. Thus, those structures can effectively prevent the short-channel effects even when the impurity concentration in the channels is restricted to a low value.
Only with a single multi-gate channel, the ON current per FET occupation area might not exceed the ON current of a regular planar-type MOSFET. Therefore, there has been a structure in which multi-gate channels are stacked in the vertical direction to obtain a sufficient ON current (see T. Ernst, et al., IEDM Tech. Dig., 2006/IEDM.2006.346955, for example). According to T. Ernst, et al., IEDM Tech. Dig., 2006/IEDM.2006.346955, Si layers and SiGe layers are alternately stacked in advance, and RIE (Reactive Ion Etching) is performed to form fins and mesas. After that, selective etching is performed to remove only the SiGe layers from the sidewalls.
The channels of those multi-gate MOSFETs are normally formed with mesa structures or fins formed on a SOI substrate or a bulk Si substrate by a lithography technique and RIE. Here, there exist two technical problems: 1) size and shape variations are caused; and 2) the widths of fins need to be reduced to approximately 10 nm or less, which is smaller than the limit in terms of lithography.
The problem of variations as the first problem can be divided into two factors. One is the shape and size variations in the plane of the substrate. The shape and size variations are caused due to the line width variation caused by the lithography and line edge roughness (LER). The other factor concerns the variation in the shapes of cross sections perpendicular to the substrate, and is caused by the variation in mesa width in the vertical direction caused by RIE. The width variations result in variations in electric characteristics such as threshold voltages, and the uneven surfaces of the sidewalls cause an increase in carrier scattering and a decrease in driving current.
To avoid the adverse influence, there are reported cases where high-temperature annealing was performed on Fin FETs having Si channels in a hydrogen atmosphere after RIE was performed. For example, a decrease in leakage by virtue of the hydrogen annealing performed on the sidewalls of Fin FETs has been reported (see W. Xiong, et al., IEEE Electron Device Lett. 25, 541 (2004), for example). This was achieved as the corners of the cross sections of fins were rounded by the surface migration of the Si atoms caused by the hydrogen annealing, and the field concentration was relaxed. An increase in ON current and a reduction in noise have also been reported (see J-S Lee, et al., IEEE Electron Device Lett. 24, 186 (2003), for example). However, this technique is also based on the surface flattening effect of the surface migration of Si atoms.
To counter the problem of the need to reduce fin widths as the second problem, sacrifice oxidation is normally performed. However, it is difficult to reduce the widths while maintaining the rectangular shapes of the fins, because of the stress in the oxide films and the dependence of the oxidation rate on the surface orientation.
By a conventional hydrogen annealing technique, however, the cross sections of the sidewalls tend to have round corners due to the surface migration. Therefore, the conventional hydrogen annealing technique is not suitable for controlling the shapes of cross sections of Fin FETs having smaller fin widths that are required in more minute CMOS. Furthermore, the effect of the hydrogen annealing to reduce the line edge roughness caused by the lithographic process is not clearly disclosed as technical information.
In a case where a conventional hydrogen annealing technique is used to form a structure having channels stacked in the vertical direction, the channel width of each upper layer differs from the channel width of each lower layer, since the shapes of the etched cross sections are not rectangular, and variations might be caused among the threshold values of the channels and the likes.
In a case where SiGe-Fin FETs or nanowire FETs are produced by performing a Ge-condensation by oxidization process on SiGe fins, the Ge composition varies with the variation in line width, and variations might be caused in ON current and threshold voltage value. Furthermore, there has not been a report that the variation in line width was reduced by flattening the sidewalls of SiGe fins by a conventional hydrogen annealing technique. As described above, to counter the problem of the need to reduce fin widths, a sacrifice oxide film is normally used. However, it is difficult to reduce the fin widths while maintaining the rectangular shapes of the fins, due to the stress in the oxide film and the dependence of the oxidation rate on the plane direction.